1. Field of the Invention
This disclosure relates to techniques for synchronizing data through different frequency domains.
This disclosure was devised with specific attention paid to its possible application for optimising the speed of a synchronization circuit comprising at least one FIFO memory.
2. Description of the Related Art
In modern integrated circuits of the System-on-Chip (SoC) type, several locally synchronous frequency domains often coexist, and they have to communicate with one another. As a matter of fact, the various modules (for example processors, audio and video decoders, memories, etc.) may operate at different frequencies, but their traffic flows converge into common channels and suitable conversions must often be performed in order to pass from one domain to the other.
In most instances, such domains are totally unrelated one to the other. For example, clock trees might be generated by different Phase Locked Loops (PLLs) or else, though being generated by the same PLL, it is not possible to infer the phase relation between each clock tree.
In these cases, the required conversion is considered to be totally asynchronous; therefore, in the interaction between two domains, it is impossible not to take into account metastability problems.
Typically, the interconnection system uses specific components, dedicated to frequency conversion. They receive input data at a given frequency (reception frequency) and they are adapted to generate the same data at a given target frequency.
In order to optimize such a flow and not to limit or jeopardize the information traffic, such components include buffering elements through which the possible “gaps” due to synchronization are eliminated or reduced.
A classical approach to going through different clock domains involves a datapath storage within FIFO memories.
As a matter of fact, a FIFO memory typically comprises a first communication interface for writing data to the FIFO memory (i.e. a write interface) and a second communication interface for reading data from the FIFO memory (i.e. a read interface). In general, such communication interfaces can operate in different frequency domains.
These FIFO memories typically comprise a circular buffer, i.e. a buffer comprising a limited number of memory locations, wherein the position following the last memory location is again the first memory location.
The write and read accesses are usually handled via a control circuit. For example, starting from write and/or read commands, the control circuit can control respective write and read pointers, which indicate e.g. respective locations for writing or reading data.
For example, Gray code pointers are normally used. Actually, the Gray code is adopted in order to enhance asynchronous communication and to avoid problems related to the sampling of asynchronous signal.
FIG. 1 shows a possible architecture of a FIFO memory 10, comprising a buffer or circular memory 12 and a control circuit 20.
For example, a write module WM can write data to memory 10 at the frequency of a first clock signal CLK1, and a read module RM can read data from memory 10 at the frequency of a second clock signal CLK2.
In order to spot the current write and read locations in memory 12, the control circuit 20 controls a write pointer, for example a Gray code write pointer, and a read pointer, for example a Gray code read pointer.
The control circuit 20 can also generate a status signal, that shows a condition in which the buffer is empty (EMPTY) and a condition in which the buffer is full (FULL). For example, to this purpose the circuit 20 can synchronize the write pointer through a chain of registers linked to the clock signal CLK2. Only after the coded pointer has gone through the synchronization chain can the write pointer be compared with the read pointer used in the domain of the clock signal CLK2.
In the meanwhile, the data item corresponding to the written location has stabilised and is ready to be read in the domain of the clock signal CLK2.